A Metal Density Improved High Speed Asynchronous Successive Approximation Register ADC
碩士 === 國立中興大學 === 電機工程學系所 === 105 === This thesis presents a high speed successive approximation register (SAR) analog to digital converter (ADC) with input buffer and the study of non-ideal situation. The design purpose of this SAR ADC is to use it as one of sub ADCs for a Time-Interleaved ADC. The...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/77v7sk |