Reducing TSV dimensions by Taguchi Method
碩士 === 國立成功大學 === 工程科學系 === 105 === Moore's Law drives the integrated circuit to continuously increase its circuit density for which 3D stacking technology is essential by the technology of through silicon via (TSV). TSV provides vertical interconnections between stacking dies. However, due to...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/db27kv |