Integration of FinFETs with Advanced Fabrication Techniques: Neutral Beam Etching, Microwave Annealing and Seedless Metallization

• Main Authors: Yin-HsienSu, 蘇映先
• Other Authors: Wen-Hsi Lee
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/ynfpu4

博士 === 國立成功大學 === 電機工程學系 === 105 === When the feature size of logic devices is scaling down toward 10 nm and beyond, current manufacturing techniques are facing a variety of challenges due to higher processing requirement. Improvement on current techniques or development of novel technology thus becomes important to keep the Moore’s law alive. In this thesis, three kinds of novel fabrication techniques are studied- neutral beam etching (NBE), microwave annealing (MWA) and seedless metallization-, and the feasibility of these techniques to be adopted in the FinFET processes are also discussed. In the first part of this study, NBE is applied to pattern high-k/metal gate MOS capacitors. Electrical characteristics of the capacitors by NBE and counterparts by a reactive-ion-etching-like (RIE-like) condition are studied, and a related plasma-induced damage model is also discussed. Results show that MOS capacitors etched by NBE demonstrated lower interface state density (Dit), oxide trap charges (Qot) and leakage current density. Furthermore, smaller capacitors etched by NBE did not lead to higher leakage current, indicating the sidewall damage was also suppressed. These results reveal that NBE is effective to prevent plasma-induced damages at the high-k/Si interface and on the sidewall and thus improve the electrical performance of the gate structure. In the second part of the thesis, MWA over a wide range of power were performed on MOS capacitors. Capacitors with rapid thermal annealing (RTA) at 500 °C are also fabricated for comparison at the same wafer temperature measured during MWA at 2700 W. For microwave annealed capacitors, key parameters such as equivalent oxide thickness (EOT), Dit, Qot, leakage current density and breakdown voltage were all improved with increasing MWA power. For the capacitor with RTA at 500 °C, diffusion of Al into TiN and growth of the interfacial oxide layer are detected, leading to the shift in flat-band voltage (VFB) and increase in EOT, respectively. Without trade-off relationship between the electrical characteristics, MWA demonstrates great potential for front-end fabrication. In the third part, FinFETs are realized by integrating NBE and MWA into the fabrication process. Sub-threshold swing of 89 mV/decade, Ion/Ioff of 10^6, DIBL of 72 mV/V and μeff of 502 cm^2V^-1s^-1 are obtained with Wfin/Lgate= 40/100 nm. These characteristics are superior by using neutral beam etching than by using RIE-like condition, and the Vt roll-off at reduced Lgate is also suppressed. A damaged layer at high-k/Si interface by RIE-like condition is observed in the TEM image, which can correspond to the degradation in electrical characteristics. Furthermore, the proportional scaling of Ion versus Wfin indicates negligible S/D resistance due to good activation by MWA. In short, functional FinFETs were fabricated by NBE and MWA for the first time, and these results pave ways for the techniques to be adopted in the advanced semiconductor processing. In the final part of this thesis, tungsten-based seedless barriers with various chemical compositions for back-end application are investigated. For CoW alloys, higher W concentration is found to be beneficial for suppressing corrosion of CoW substrates and also improving the thermal stability. However, on the surface of Cu/CoW films with high W concentration, Cu agglomeration and pin-holes were found after annealing, indicating poor adhesion between Cu and high-W-content CoW alloys. These results indicate a trade-off relationship between barrier properties based on W concentration. CoW alloys with moderate W concentration around 50% are found to be a direct platable material which also demonstrates desirable adhesion and anti-diffusion characteristics for the sub-20 nm metallization process.