Design for Clock and Data Recovery Circuits and Quick Estimation for Jitter Tolerance
博士 === 國立成功大學 === 電機工程學系 === 105 === Demands for Serializer and De-serializer (SerDes) integrated circuits (ICs) have increased due to the widespread use of Ethernet networks and chip-to-chip interfaces. To ensure the input data stream is well recovered in a receiver end, the clock and data recovery...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54b6nm |