Analysis of the Multi-Vt FD-SOI MOSFETs and SRAM Application
碩士 === 國立成功大學 === 奈米積體電路工程碩士學位學程 === 105 === As CMOS technology industry continues to scale, especially at sub 22 nm node, many physical limitations mostly related to short channel effect (SCE), such as drain-induced barrier lowering and hot carrier effect, have surfaced. The mainstream solution is...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/z8s355 |