Architectural Optimization for a Quad-Core Java Processor
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 105 === This thesis is developed based on a quad-core Java Application IP (JAIP-MP). We change the bus protocol from PLB to AXI4 and use two different controllers to solve the coherence problems, which appeared after the protocol modification. The first controller, c...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/rv2rvr |