Design of Low-Voltage-Trigger SCR for ESD Protection in 28nm CMOS Process
碩士 === 國立交通大學 === 電子研究所 === 105 === With advanced CMOS technology, CMOS devices have been fabricated with thinner gate oxide, and the operation ability of integrated circuits can attain to high speed and low power consumption. However, with the scaling of CMOS technologies, the ESD robustness decrea...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33171201008431051012 |