A 5 Gbps Dual Path Clock and Data Recovery with Capacitor-Amplified Technique and Adaptive Loop Gain Controller
碩士 === 國立中央大學 === 電機工程學系 === 105 === As CMOS technology continues to advance, the computing capabilities of integrated circuits are expanding, and the fast serial link technologies have received significant attention in the recent past. The clock and data recovery (CDR) is the crucial role of receiv...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61580678442869799760 |