A 5 Gbps Dual Path Clock and Data Recovery with Capacitor-Amplified Technique and Adaptive Loop Gain Controller

• Main Authors: Po-Min Cheng, 鄭柏旻
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/61580678442869799760

碩士 === 國立中央大學 === 電機工程學系 === 105 === As CMOS technology continues to advance, the computing capabilities of integrated circuits are expanding, and the fast serial link technologies have received significant attention in the recent past. The clock and data recovery (CDR) is the crucial role of receiver timing circuits in the serial link systems, and achieves to optimally sample the input data with various timing jitter profiles. Due to increasing of the data rate, the timing budget of the CDR becomes very tight and makes it more difficult to guarantee the required Bit-Error-Rate (BER) and the jitter tolerance (JTOL). This study takes USB 3.0 specification as reference material, and presents a dual path clock and data recovery with adaptive loop gain controller (ALGC) and capacitor-amplified technique (CA). The ALGC enhances the jitter performance and JTOL by detecting the jitter frequency spectrum and controlling loop gain adaptively, and the enhanced percentage of low and high frequency input jitter is about 50% and 12%, respectively. To reduce the area of loop filter, the CA is utilized in the integral path to count the output signal of the bang-bang phase detector, and the reduced percentage of area is about 50% without lowering system stability. The test chip was fabricated by a 90-nm standard CMOS process with a 1-V supply and the core area occupies 0.073 mm2. The measured jitter of the recovered clock is 3.2 psrms and 26.4 pspp, and the power consumption is 16.8 mW at the 5-Gbps data rate.