An All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application
碩士 === 國立中央大學 === 電機工程學系 === 105 === With the flourishing of consumer electronics, Central Processing Unit (CPU) has to be operated in higher frequency to meet the higher quality requirement. The Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) as the important peripheral of CPU...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/13497222405046585211 |