Chip Design of an 8-bit Low Power High Speed Sub-range ADC Based on a PMOS Digital Comprartor Architecture
碩士 === 國立彰化師範大學 === 資訊工程學系積體電路設計碩士班 === 105 === In this thesis, we designed an 8-bit Sub-range Analog to Digital converter (ADC). The sub-range ADC consists of a 6-bit coarse ADC and a 2-bit fine ADC. By using a specially designed architecture of PMOS comparators, the proposed ADC attains a higher i...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84cpuc |