| Summary: | 碩士 === 國立清華大學 === 光電工程研究所 === 105 === In the recent years, high indium content InGaAs-based HEMTs have high potential for high-speed and low-power logic application. 90 nm gate length InAs-channel high electron mobility transistors (HEMTs) have then been fabricated with success and characterized for high-frequency and low-power logic applications. The logical performance of the InAs-channel HEMTs was improved by using advance techniques.
In this thesis, the indium content is used and one hundred percent of the InAs-channel were grown on lattice match In-P substrates. The 90 nm InAs HEMTs processed with field plate techniques, Ti/Pt/Au non-alloyed ohmic process, two-step recess and Pt gate sinking technologies for logic applications were fabricated. Depletion and Enhancement Mode InAs Channel HEMTs of the developed 90 nm InAs HEMTs with these advanced processes perform better than the traditional InAs HEMTs at low applied voltage, for example: better current saturation, lower output conductance (go), lower negative threshold-voltage (VT) , smaller subthreshold swing (SS). The excellent electronic performances indicate that the developed 90 nm InAs HEMTs are suitable for high-speed and low voltage applications.
In this thesis, the fabrication of 90 nm InAs-channel HEMTs using field plate was developed. We have demonstrated that the field plate technique can realign the electrical field distribution to improve device performance. The devices show great performance in low applied voltage (VDS=0.5 V). The drain induced barrier lowering (DIBL) is 44 mV/V, subthreshold swing (SS) is 64.1 mV/decade, ION/IOFF ratio achieved 2.4 × 104, and much higher breakdown voltage achieved 8.3 V. These results show that the field plate technologies substantially improve logic device performance. Therefore, it has great potential for high-speed and low-power logic application for the next generation.
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