A Delta-Sigma Phase Locked Loop working at 9 ~ 11 GHz
碩士 === 國立清華大學 === 電機工程學系所 === 105 === In such an era that IC technology develops rapidly, generating clock signals in a system is a very important topic. One of the common methods is the Phase Locked Loop (PLL). PLL can generate an very accurate clock signal. Following is the operating principle of...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/pc4f22 |