A Collaborated Stochastic LDPC Decoder Architecture with Effective Probability Tracer
碩士 === 國立清華大學 === 電機工程學系 === 105 === This thesis presents an efficient collaborated stochastic low-density parity-check (LDPC) decoder, where a bit-flipping (BF) based collaborative decoder is used to achieve less decoding cycles without degradation in bit-error-rate (BER) performance. A node-wise...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64dynf |