A Leakage-Current Sensor Enhanced Memory BIST for Defect Level Reduction

• Main Authors: Lu, Wei Hao, 呂偉豪
• Other Authors: Wu, Cheng Wen
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/z86357

碩士 === 國立清華大學 === 電機工程學系 === 105 === Semiconductor memory is considered an essential component in almost all electronic systems. Increasing the yield and reliability of semiconductor memory becomes a more and more important issue. It is well known that in advanced process technologies, more and more defects in an IC cannot be modeled and tested by conventional logic-level faults or voltage measurements at the primary outputs. Delay (timing) testing and current measurement, e.g., are two important approaches, which help cover such defects that may otherwise escape conventional tests. Delay or at-speed test is relatively mature, but a complete test that covers all potential timing defects can be slow and impractical for large memories, so we address the issue using a current measurement circuit (current sensor). Memory built-in self-test (BIST) is popular and mature for embedded memories, especially for static functional faults. For timing related dynamic defects, however, complicated test algorithms and clock schemes may be required. Even if they can be executed at-speed, the process still can be too slow and impractical for large embedded memories. We try to address the issue by integrating a current sensor with the existing BIST design. We reuse the current sensor circuit developed by Prof. Ying-Chieh Ho of NDHU, who provides the current sensor circuit and layout. Based on that, we propose a leakage-current sensor enhanced memory BIST for reducing defect level of embedded RAM, where the original memory BIST was generated by BRAINS (BIST for RAM in seconds). The leakage-current sensor mirrors the leakage-current from the circuit under test, and then quantizes the result into a digital form that is to be evaluated by the BIST circuit. We use a commercial 65nm CMOS technology (with standard cell library) to implement the memory BIST design, and use a commercial SRAM compiler to generate an 8KB (2048x32 bits) single-port SRAM. As an experiment, we integrate the memory BIST, SRAM, and the leakage-current sensor into a single test chip, and finish the design at the physical level. Based on detailed post-layout simulation, we conclude that the leakage-current sensor enhanced memory BIST works as we expected. However, the extra loading of the current sensor to the SRAM results in a lower measurement current than expected, but this factor can be taken care of in the calibration process (to determine the reference current) before mass production test. The reference current will then be entered into the BIST module in the beginning of the test session for go/no-go comparison with the measured current. In summary, the proposed leakage-current sensor enhanced memory BIST can do the original functional test, and furthermore it can sense the leakage-current of the SRAM. The minimum value of the current detected by our design is 30 uA. The total area of our design is 905x905 um2.