Error Correction of Schematic Extraction from Microwave Multilayer Layout and Three-dimensional Graphical User Interface
碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === In this thesis, a graphical verification tool is developed for microwave multilayer passive circuits, which are usually designed by hand, and cannot be verified by the existing layout versus schematic checker. We''ve surveyed the studies accom...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/8pjtx2 |