| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === In this thesis, a graphical verification tool is developed for microwave multilayer passive circuits, which are usually designed by hand, and cannot be verified by the existing layout versus schematic checker. We''ve surveyed the studies accomplished by our laboratory and revised the previous algorithms. With the existence of the layout to schematic extraction and the circuit netlist mapping program, this thesis is dedicated to
the combination of them. This tool also supports three-dimensional display. The purpose is to reduce the time cost of mistakes and help users to verify the circuit. However, for different designers, like their personal habits or a lumped component in small value, the program is still unable to determine the layout to schematic mapping accurately.
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