Digital Phase-Locked Loop With Background Supply Noise Calibration and Injection-Locked Clock Multiplier
碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === This thesis consists of two parts. The first part implements a digital phase-locked loop (DPLL) with background supply voltage sensitivity calibration. A digital supply voltage sensitivity controller with a frequency subtractor is used to suppress the supply vo...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/k3n9vy |