| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === This thesis consists of two parts. The first part implements a digital phase-locked loop (DPLL) with background supply voltage sensitivity calibration. A digital supply voltage sensitivity controller with a frequency subtractor is used to suppress the supply voltage sensitivity. With a 50mVPP, 100kHz sinusoidal supply noise tone, the calibration scheme reduces the peak-to-peak jitter from 41.48ps to 23.15ps and the rms jitter is reduced from 7.26ps to 3.47 ps. The measured peak-to-peak jitter and rms jitter without supply noise are 19.21ps and 2.71ps. Its active area is 0.006mm2 and the power consumption is 9.34mW.
The second part implements an injection-locked clock multiplier (ILCM). The ILCM is presented with a frequency calibrator (FC) using a delay time detector to calibrate the frequency error due to the process, voltage, and temperature (PVT) variations. The reference spur and timing jitter due to the PVT variations can be significantly reduced. When injection locked, the measured reference spur is -61.28dBc and the rms jitter integrated from 10kHz to 100MHz is 479fs. Its active area is 0.012mm2 and the power consumption is 2.55mW.
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