Signal Integrity Design for High Speed SerDes Interface in Wafer Level Package
碩士 === 國立臺灣大學 === 電信工程學研究所 === 105 === This thesis presents power and signal integrity model for high speed SerDes interface operating at 25 Gbps. High speed SerDes interface includes 4 Gbps high speed single end parallel signal and 25 Gbps differential serial signal. This research is divided into t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/546tzf |