| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 105 === This thesis presents power and signal integrity model for high speed SerDes interface operating at 25 Gbps. High speed SerDes interface includes 4 Gbps high speed single end parallel signal and 25 Gbps differential serial signal. This research is divided into three sections.
First, establishing high speed parallel signal circuit model and analyzing the signal eye diagram on the receiving end. Presenting methods to increase receiving end signal eye diagram by decreasing cross talk noise and normalized resistance. Comparing with the original design, successfully increased layout length by 8 mm while increasing 35% the maximum bandwidth. Giving each layout design’s cross sections and maximum bandwidth relational graph for designers to design the most suitable layout.
Second, design the high speed differential serial signal with a passive equalizer and FIR equalizer for faster selection to compensate the loss in channel. Thus increasing the integrity of the signal and exploring the limits of the equalizers. Through the eye height design, operating at 25 Gbps increases by 20%, 50 Gbps increases by 43% and using FIR equalizer to compensate 25 Gbps scaling down high speed differential serial signal by line width 0.5 μm increases layout length by 110%. Also, using PCB scaling up model to verify eye diagram simulation results and testing its accuracy.
Lastly, presenting the power delivery network model. Aiming at the ground bounce noise of high speed SerDes interface extracting parameter with simulation software, which will be of great help in prediction and analyzing simulations for future signal / power integrity.
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