SDNoC-Based AES Accelerator for Network-on-Chip
碩士 === 國立臺灣科技大學 === 電子工程系 === 105 === Network-on-Chip (NoC), which is a packet-based and multi-core architecture. It is considered to be a new generation of SoC and the solution for the interconnection problem of large-scale SoCs. Most AES related publications not designed for NoC could suffer the l...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/07471712075335859244 |