5.5GHz Fast Lock All Digital PLL Design
碩士 === 國立臺灣科技大學 === 電機工程系 === 105 === This thesis presents a phase-frequency error compensation mechanism for an all digital phase-locked lopp(ADPLL). First a novel digital-controlled oscillator(DCO) was designed. Eleven pairs of symmetrical PMOS varactors are connected in parallel in the tank circu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/garc85 |