A Modified BAST for Test Data Reduction Using Correlation of ATPG Pattern
碩士 === 南臺科技大學 === 電機工程系 === 105 === In order to reduce the test data for BAST (BIST-Aided Scan Test), an LFSR reseeding circuit with additional MUXs (Multiplexer) and NOT gates are proposed. The procedure to generate the control signals for optimal reseeding of the circuit are proposed by making co...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/5u939p |
| Summary: | 碩士 === 南臺科技大學 === 電機工程系 === 105 === In order to reduce the test data for BAST (BIST-Aided Scan Test), an LFSR reseeding circuit with additional MUXs (Multiplexer) and NOT gates are proposed.
The procedure to generate the control signals for optimal reseeding of the circuit are proposed by making correlation tables based on matching between PRPG (Pseudo Random Pattern Generators) pattern and ATPG (Automatic Test Pattern Generation) pattern slice.
I enhanced the structure of the LFSR by adding extra MUXes and NOT gates based on correlation table of ATPG pattern. A reseeding method for the enhanced LFSR is also proposed. MUXes are added based on correlation table of ATPG patterns. To select position of extra MUXes, a suitable correlation table is chosen by the normalized value of the correlation tables (same, different, don't care).
Experimentation and evaluation of test data volume for ISCAS89 and ITC99 benchmark circuit are conducted. I applied the proposed procedure for 13 benchmark circuits. The procedure can achieve about 15-56% reduction in test data for BAST.
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