Baseband Clock and Data Recovery Circuit for Dedicated-Short-Range-Communications Systems
碩士 === 元智大學 === 電機工程學系 === 105 === This thesis shows the Basic Clock and Data Recovery circuit which is applied to the short-range communication system. This circuit uses the All Digital Phase Locked Loop structure to reduce the layout area and to change the circuit parameters much easier. Because t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/v9w23g |