Reconfigurable Decoding Kernel Designs and Implementations of Turbo and LDPC Codes for Powerline Communication Standards
碩士 === 元智大學 === 電機工程學系 === 105 === This thesis presents reconfigurable decoding kernels for turbo/low-density parity-check (LDPC) code for powerline communication systems. Here presents two architectures and both of them are using radix-4 double binary enhanced max-log maximum a posteriori probabili...
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| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/f3kc9f |