Reconfigurable Decoding Kernel Designs and Implementations of Turbo and LDPC Codes for Powerline Communication Standards

• Main Authors: Jin-Kun Shen, 沈晉堃
• Other Authors: Cheng-Hung Lin
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/f3kc9f

碩士 === 元智大學 === 電機工程學系 === 105 === This thesis presents reconfigurable decoding kernels for turbo/low-density parity-check (LDPC) code for powerline communication systems. Here presents two architectures and both of them are using radix-4 double binary enhanced max-log maximum a posteriori probability algorithm with next iteration initialization in turbo decoding. In LDPC decoding, these works employ the normalized Min-Sum algorithm and the layered based radix-4 forward and backward algorithm. Due to the two algorithms may make differences in architecture and throughput rate. Therefore the proposed decoding kernels have the different architectures in combining the turbo decoding algorithm. However, the proposed two decoding kernels each have its own advantages and disadvantage in trade throughput off against the area. In order to make these kernel’s features obviously, we propose a new algorithm and some well-structures that lead to significant throughput gains and better area efficiency compared to distinct works. The proposed decoding kernels can be operated in all of the modes specified in HomePlug and G.hn standards and implemented using a 40-nm CMOS process. In addition, the proposed decoding kernels provide differences solutions to achieve the expected throughput rates of G.hn and HomePlug standards.