Improve DRAM leakage using Theory of Inventive Problem Solving (TRIZ) method

• Main Authors: Lo, Kuei-Li, 羅貴利
• Other Authors: WANG,CHIEN-CHIH
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/p59ttb

碩士 === 明志科技大學 === 工業工程與管理系碩士班 === 106 === Buried field - effect transistor is popularly used for modern DRAM design because of its superiorities in drain-induced barrier lowering (DIBL), sub-threshold slop and junction leakage. However, gate induced drain leakage (GIDL) is enhanced by large source-drain overlap gate area. It leads the leak of storage capacitance used spontaneously resulting in the short and variable data retention time in the manufacturing of DRAM. The minimization of leakage current and maximization of device performance by favorable doping profile of source and drain are always the focus in the manufacturing process. The small but sufficient area of source-drain overlap with large depletion region is the desirable doping profile. However, it accompanies with disadvantages of higher source-drain contact resistance and lack of carriers. To analysis GIDL by using TRIZ methodology to find the key dis-advantage and way of solution, to use 40 inventive principles and Patent/Knowledge search learnt from ex-knowledge, DOE by domain knowledge with suggested direction and verify the solution.