Debug System for ESL Design and Trap Handler Architecture on CASLAB-GPU
碩士 === 國立成功大學 === 電腦與通信工程研究所 === 106 === Electronic System Level (ESL) design let developers fulfill hardware co-simulated with software in early design stage of SoC platform. In order to have an efficient design with testing, building a debug system on simulation platform is necessary. It can be di...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/zf86hd |