Study of Tri-Gate InAs HEMTs for Low-Noise Amplifier Applications

• Main Authors: Huang, Zhi-Yi, 黃至毅
• Other Authors: Chang, Edward-Yi
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/23ttw8

碩士 === 國立交通大學 === 光電系統研究所 === 106 === Recently, the planar transistors with sub-micro-scale gates have already been the trend of semiconductor industry. Many researches still focus on reducing gate length. However, as the transistor scales down, many problems start appearing, such as VTH roll-off and off-state leakage, or so called short channel effect. Therefore, searching a new channel material and a corresponding fabrication process are urgent to improve the device characteristics. InAs channel lattice possesses with high electron mobility and low threshold voltage. It matches with InP substrate as well. As a result we use InAlAs/InAs/InP high electron mobility transistors (HEMTs) to achieve high-speed and low power consumption in this study. Furthermore, by double electron beam lithography and etching, 3-D structure HEMTs that increase the area between gate and channel has been successfully fabricated. This study also compared electrical characteristics between 3-D and planar devices. The results show that the 3-D devices has better gate controllability, not only improving logic performance likes SS and ION/IOFF ratio, but also increase GM (VDS=0.5V). When VDS increases to 1V, the subthreshold characteristics and Ion/Ioff ratio are further improved, resulting in better noise performance. Compared to planar device, not only Associated Gain (dB) has been improved, but also Noise figure is reduced. These results demonstrate that Tri-Gate InAs HEMTs are suitable for high-frequency and low noise applications.