Priority Scheduler Circuit Design for Multi-core Java Processor
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 106 === We implement a quad-core Java Application IP(JAIP-MP) with multi-level priority scheduler in this thesis and integrate Power-on Bootup Logic(POBL) into JAIP-MP SoC to bootup system. We propose a two-level hardware scheduler which is global and local. Inter-co...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/7p3t6f |