Timing-driven layer assignment
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 106 === As the development of very-large-scale integration (VLSI) circuit continues to advance, the feature size scales down to nanometer-level. The width of a metal wire used in a circuit also decreases, which increases the metal resistance and thus the interconnect...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/7vbvfc |