Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 106 === Circuit performance has been the key design constraint for over a decade. Varia-ble-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72juy6 |