Evaluation of the Various Scaling Routes on Novel Poly-Si Junctionless Transistors
碩士 === 國立交通大學 === 電子物理系所 === 106 === For the demands and developments of semiconductor industry, the device dimension is scaled down continuously. In this dissertation, we investigate the pros and cons of the multi-gate poly-Si junctionless transistors in the various scaling routes. The routes are c...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t3jn55 |