| Summary: | 博士 === 國立交通大學 === 電信工程研究所 === 106 === Iddq testing has been used for decades to identify potential defective chips because the measurement results of those chips are out of the electrical range. Pre-defined threshold values from design specification overlooks the influence of process variations, and the threshold values defining from early-production chips may lose the predictability in future mass production. The main issue of the threshold-based Iddq testing is lack of the controllability of variations during fabrication process. Therefore, the thesis aims at developing the next-generation Iddq testing, which considers the variation in manufacturing. The concept of variation-aware Iddq testing is to remove all possible variabilities during testing, such as process variations and the number of Iddq tests. Therefore, a variation-aware Iddq testing is proposed to eliminate the process variations with a variant-aware full-chip leakage model. With the process-free Iddq, the defective chips can be filtered out and the suspect short candidates can be marked in the defective chips. To combat the limitation of test number on Iddq testing, a probability-based thresholding is developed. The variation-aware Iddq testing and diagnosis are evaluated with various conditions, such as the different amount of process variations, the influence of test pattern counts, and the impact of chip size. However, the measurement noise from tester and unknown leakage sources are big concerns in variation-aware Iddq testing. Therefore, we propose the development of an on-chip process monitor targeting few process parameters to reduce the impacts of measurement noise from the tester. In the thesis, a data analysis is applied to explore the dominant timing process parameters and dominant leakage process parameter: supply voltage, chip temperature, effective gate length, and gate oxide thickness. We believe that the design of on-chip process monitor with the four process parameters can eliminate the effect of measurement noise to improve the variation-aware Iddq testing. Meanwhile, the on-chip process monitor can also estimate the actual timing within the chip. Since the number and the location of on-chip process monitor need to be designed to consider the intra-die variation, and shall be design-dependent. The development of general-purpose on-chip process monitor becomes a future work of this research. In addition, the implementation on applying the variation-aware Iddq testing and diagnosis, and the application on other parametric testing methods are also the future works of this thesis.
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