Machine-Learning Based Failure Binning for Debugging RTL Designs
碩士 === 國立交通大學 === 電機工程學系 === 106 === Verification and debugging have become the major pain-point in Register Transfer Level (RTL) design as design size and complexity increase. If there is a functional bug in RTL design, numerous and diverse failures would be exposed in the regression test. To diagn...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/8emha2 |