| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 106 === Verification and debugging have become the major pain-point in Register Transfer Level (RTL) design as design size and complexity increase. If there is a functional bug in RTL design, numerous and diverse failures would be exposed in the regression test. To diagnose and fix design errors more efficiently, categorizing and prioritizing these failures is necessary. In this work, a machine learning based failure binning engine is proposed. First, the engine will collect failures from testbench simulation, and then try to explore suspect elements by SAT-based debugging technique. Next, a suspect data weighting scheme is defined to represent failures by a feature-based matrix. Finally, an advanced machine learning based clustering algorithm is applied to obtain the failure bins with respective confidence rank. Experimental results show the failure binning engine demonstrates an overall accuracy of 90% that obtains high-quality bins with the accurate confidence ranking.
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