Design of 10-bit SAR ADC with Background Calibration of Comparator Offset
碩士 === 國立交通大學 === 電機工程學系 === 106 === This thesis presents a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with background calibration of comparator offset. A pre-amplifier is used as the first stage of the comparator. As there is mismatch between input differential...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/bvh4gu |