A Reinforcement Learning Based Logic Synthesis Framework for Further Area Optimization
碩士 === 國立清華大學 === 資訊工程學系所 === 106 === It is well-known in the industry that the outcomes of Electronic Design Automation(EDA) tools can be further fine-tuned by carefully trimming gate-level cell library at logic synthesis stage. With better selections of library cells, the Synopsys Design Compiler...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/r2v34g |