A low power 10bit 200Ms/s Pipelined ADC
碩士 === 國立清華大學 === 電子工程研究所 === 106 === A 10-bit 200-MS/s pipelined analog-to-digital converter (ADC) using virtual ground reference buffer and foreground calibration technique in TSMC 0.18μm standard CMOS process technology is presented. The simulated ADC performances achieve -85 dB of Noise Level ,...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/h244uc |