Accelerated Locking Scheme for Super-Wide Range Delay Line
碩士 === 國立清華大學 === 電機工程學系所 === 106 === In today's system-on-a-chip (SOC), microprocessors, communication ICs, and other time-related circuit designs, Delay-Locked Loops (DLLs) and Phase-Locked Loops (PLLs) are widely used to eliminate the clock skew. In advanced COMS processes where supply volta...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/5r9w8d |