ATPG and Test Compression for Probabilistic Circuits
碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Probabilistic circuits are gaining importance in the next generation ultra low-power computing and quantum computing. Unlike testing deterministic circuits, where each test pattern is applied only once, testing probabilistic circuits requires multiple pattern...
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| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/2vm53r |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Probabilistic circuits are gaining importance in the next generation ultra low-power computing and quantum computing. Unlike testing deterministic circuits, where each test pattern is applied only once, testing probabilistic circuits requires multiple pattern repetitions for each test pattern. However, previous test pattern selection techniques require long test length so it is time consuming. In this thesis, we propose an ATPG algorithm for probabilistic circuits. We use specialized activation and propagation methods to reduce pattern repetitions. Also, we propose to accumulate contribution among different patterns to further reduce pattern repetitions. Experiments on ISCAS’89 benchmark circuits show the total test length of our proposed method is 34% shorter than a greedy method [Chang 17].
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