Ferroelectricity-Based Transistors for Steep Subthreshold Swing Application

• Main Authors: Pin-Guang Chen, 陳品光
• Other Authors: Ming Han, Liao
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/h3s5kv

博士 === 國立臺灣大學 === 機械工程學研究所 === 106 === The internet of things (IoT) and wearable applications become more popular in recent years, therefore, it has become necessary to develop small sized, high performance devices, with low power consumption. In GaN based MOS-HEMTs, the subthreshold swing (from 4V/dec to 2V/dec) and peak gm (18.4% enhancement) improvement of ferroelectric negative capacitance AlGaN/GaN-on-Si MOS-HEMTs has successfully demonstrated. The gd at almost zero VDS and the linear current showed 33% and 23% enhancement, respectively, with NC(negative capacitance) caused by the internal voltage amplification. Indium-based ternary barrier HEMTs on Si substrate are demonstrated using In0.18Al0.82N (6.4nm)/AlN (2.2nm)/ GaN-on-Si for high power applications. Compared with AlGaN based HEMTs, a high ON/OFF ratio of ~ 107 and a steep subthreshold swing of 67 mV/dec are obtained due to high polarization and a lower lattice mismatch compared to GaN. When compared with the control InAlN/AlN/GaN-on-Si MIS-HEMTs with Ohmic contacts, the OFF current was reduced by one order of magnitude using Schottky-drain contact technology. A steep subthreshold swing below 100 mV/dec of the InAlN device was obtained as a result of high polarization and a lower lattice mismatch with GaN. Planar FE-HZO FETs is experimentally demonstrated with CET=0.98nm, a small hysteresis window△VT<0.1V, SSfor=42mV/dec, SSrev=28mV/dec, and switch-off <0.2V. The optimum ALD process leads single monolayer SiOx for IL and low gate leakage current. The first NC-FinFET is reported in 2015 IEDM. We verified the 5nm FE=HZO on FinFET platform, the minimum subthreshold swing of P-tpye NC-FinFET is SS=55mV/dec (top gate) and SS=87mV/dec (internal gate) at room temperature. The minimum subthreshold swing of N-tpye NC-FinFET is SS=58mV/dec (top gate) and SS=88mV/dec (internal gate) at room temperature. In 2016 IEDM, we reported ultrathin FE-HZO (1.xnm) FETs. The ultrathin FE-HZO FETs with RTA 700°C observe the superior characteristics SSmin=52 mV/dec and hysteresis free (ΔVT = VT, for – VT, rev =0.8 mV). The ferroelectric Al:HfOx FET demonstrates SS=40 mV/dec and 39 mV/dec for forward and reverse sweep, respectively, and it is hysteresis-free. The partial orthorhombic phase of FE-HAO is confirmed with and without a capping layer. We successfully demonstrated the steep slope FETs (subthreshold swing below 60mV/dec at room temperature) on Si and GaN with a ferroelectric gate stack. To overcome the limit of 60mV/dec is an important breakthrough for next generation CMOS.