Design and Implementation of 12-bit Sub-ranged SAR ADCs
碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === This thesis is aimed to present 12-bit Sub-ranged successive approximation register (SAR) analog-to-digital converters (ADCs). In order to speed up the sampling rate, the ADC architecture is proposed using the subrange SAR operation. Besides, by applying a new d...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/cq776s |