Design and Implementation of 8-bit Ultra-High-Speed SAR ADCs
碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === This thesis implements two 8-bit ultra-high speed successive approximation register (SAR) analog-to-digital converters (ADCs). Based on SAR operation, to improve the sampling rate, the new proposed architecture uses Domino operation to reduce the delay between t...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/4fk998 |