Analysis on Pad Performance for Chemical Mechanical Polishing/Planarization of Shallow Trench Isolation

• Main Authors: Shih-Yao Wang, 王詩堯
• Other Authors: Chao-Chang A. Chen
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/6x27u4

碩士 === 國立臺灣科技大學 === 機械工程系 === 106 === Chemical mechanical planarization/polishing (CMP) has been widely adopted in the integrated circuit (IC) fabrication. Due to demand of IC downsizing to nanoscale, CMP process stability and reproducibility continue to face stringent challenges. Polishing pad surface topography is one of the major factors for determination on wafer planarization, which pad polishing efficiency index (PEI) can be considered as one of quantification of pad surface performance in CMP process. This study is to develop PEI based on the interfacial area ratio (Sdr) and related root-mean-square surface roughness(Sq) and (Spk). The PEI is (Sdr) defined by the ratio between multiplication of the interfacial area ratio and reduced peak height (Spk) dividing to the root mean square height (Sq). Finally, the shallow trench isolation (STI) CMP process is used to verified by PEI. The CMP process of silicon oxide (SiO2) and silicon nitride (Si3N4) film wafers has been verified to identify the correlation between the pad PEI and material removal rate (MRR) of oxide and nitride film wafer. Experimental results show that the PEI increases as with MRR of oxide wafer increasing and also as decreasing wafer surface topography. Thus the PEI can be used a pad performance index for STI CMP process based on current configuration of this study. Results of this study can be further adopted as an index for in-situ monitoring of pad topography for process control of STI CMP for advanced node IC demands.