A 10-bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with Charge-Pump Phase-Locked Loop
碩士 === 國立臺北科技大學 === 電機工程系 === 106 === This thesis presents a successive approximation register analog-to-digital converter (SAR ADC), which is fabricated in TSMC 0.25μm 1P3M CMOS high-voltage process for electric car. There are two chips were designed, in this thesis, the first chip(chip1) is a 10-b...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/r868q2 |