Analysis and Integrated Circuit Layout of EEG Analog Front-end Circuits
碩士 === 中華大學 === 電機工程學系 === 107 === The purpose of this thesis is to design a better efficiency EEG analog front-end circuit with compact size. We used the UMC 0.18um 2P6M CMOS process provided by National Applied Research Laboratories (NAR Labs) / Taiwan Semiconductor Research Institute (TSRI) to...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92h33p |