A Deep Reinforcement Learning Based Logic Synthesis Framework for Further Area Optimization
碩士 === 逢甲大學 === 電子工程學系 === 107 === It is very well-known in the industry that the Synopsys Design Compiler can achieve better area reduction while maintaining given design constraints by carefully selecting a smaller target gate-level cell library from primitive one at synthesis stage. The selecting...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/a3934e |