| Summary: | 碩士 === 國立中興大學 === 資訊科學與工程學系所 === 107 === The technological advancements on integrated circuits (IC) drive the increasing of wafer size as well as the number of dies that can be put in a wafer. As a result, the costs of testing and retesting wafers also increase.
Wafer test is divided into probing and re-probing phases. Wafer probing phase is for checking the quality of each die in the wafer. Wafer re-probing phase only retests the failed dies discovered in the probing phase. To do chip probing on a wafer, the probes on the probe card need to make contact with wafer for electrical testing (In-Circuit-Test). This process is called Touch-Down. Re-probing is a free service without charge for an IC packaging/testing company. Therefore, reducing the number of touch-downs can reduce the costs of wafer testing. This is the issue that we try to solve in this thesis.
By analyzing the distribution of failed dies in a wafer after the probing phase, this thesis propose two methods for reducing the number of touch-downs to generate new site maps for re-probing. One is an improved traditional method, and another one is a greedy method. The experimental result shows that comparing to the traditional method, the proposed improved traditional method and greedy method can reduce the number of touch-downs to 8% and 15% in average, respectively. And the best reduction rates are 16% and 23%, respectively. The reduction in the number of touch-downs can also reduce the maintenance costs of probe cards in addition to increasing the productivity.
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